Search Patents
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Calculator with stepwise display of linear equations
Patent number: 5732001
Abstract: An improved educational calculator permits sequential display of equations as transformations are made to solve the equations.First simultaneous linear equations are entered, and each time an advance key is depressed, process equations, obtained by transforming the equations step by step to reach their answers, are successively displayed on a liquid-crystal display screen. Each time a return key is depressed, the process equations are successively displayed from the answers to the equations in a reverse manner. The problem-solving method is selected through the entry of a solution key among the addition and subtraction method, the substitution method and the equivalence method, which are learned in the junior high school. The sequential display mode of the process equations can be switched between the automatic sequential display and the display on the basis of each entry of the advance key and the return key.
Type: Grant
Filed: August 31, 1995
Date of Patent: March 24, 1998
Assignee: Sharp Kabushiki Kaisha
Inventors: Hitoshi Nakayama, Syuji Uemura
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Graphic processing apparatus, graphic processing system, graphic processing method and graphic processing program
Publication number: 20050259100
Abstract: A graphic processing apparatus, comprising: a plurality of stamp information storages provided corresponding to a plurality of line equations, respectively, capable of storing values obtained by inputting coordinates relating to a stamp including a plurality of pixels adjacent to each other to the corresponding line equation; a plurality of information selectors provided corresponding to said plurality of line equations, respectively, which select alternately one of information stored in said plurality of stamp information storages; a plurality of linear equation calculators provided corresponding to said plurality of line equations, which input coordinates relating to a current stamp to the corresponding linear equation based on information selected by said information selectors in order to calculate a value of the corresponding linear equation, and store the calculation results in the corresponding stamp information storage; inside/outside determination unit configured to determine whether or not a subseque
Type: Application
Filed: September 30, 2004
Publication date: November 24, 2005
Applicant: KABUSHIKI KAISHA TOSHIBA
Inventor: Tatsuo Teruyama
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Apparatus and method for calculating square root
Publication number: 20070083587
Abstract: An apparatus and method for calculating a square root are provided. The square root calculation apparatus calculates an approximated square root for an input value. An integer detector detects a position of a non-zero most significant bit (MSB) from the input value, and outputs an arbitrary integer value. A first approximated linear square root calculator outputs an approximated square root by applying the input value and an even integer value output from the integer detector to a first linear approximation equation. A second approximated linear square root calculator outputs an approximated square root by applying the input value and an odd integer value output from the integer detector to a second linear approximation equation. A controller controls a multiplexer such that the approximated square roots calculated by the first and second approximated linear square root calculators are output according to whether the integer value output from the integer detector is an even number or an odd number.
Type: Application
Filed: July 31, 2006
Publication date: April 12, 2007
Inventors: Hee-Jin Roh, Gang-Mi Gil, Min-Goo Kim, Hyun-Seok Oh
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User programmable postal rate calculator
Patent number: 4495581
Abstract: A calculator for determining postage or shipping fees which has a bus-oriented microprocessor structure having several memories, including a read only memory with programmed quadrangles corresponding to geographic areas represented by the three most significant digits of ZIP codes. This memory allows a computation of a distance-related value to be performed for each shipment between a destination ZIP code and an originating ZIP code. The distance-related value is converted to a zone by means of a look-up table. The zone, as well as a carrier selection, define a piece-wise linear curve to be used for fee calculation. Using an equation related to distance and having weight of a parcel defined by a scale, on which the parcel rests, the shipping fee may be calculated. Once the fee is calculated, special services may be added.
Type: Grant
Filed: October 19, 1981
Date of Patent: January 22, 1985
Inventor: James M. Piccione
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Control method, controller, recording medium recording control program, numerical calculation method, numerial calculator and recording medium recording numerical calculation program
Publication number: 20040167951
Abstract: A·U+B(U)=f, wherein A is a linear differential operator, B is a nonlinear differential operator, and f is an inhom*ogeneous term (source term) in a nonlinear partial differential equation to be satisfied by a physical quantity U, is solved by successive approximation. In calculation, (f−A·Um−B(Um)) is given as a nonlinear residual rr of an approximate solution Um, wherein m is the number of repeating times, and the approximate solution Um is repeatedly corrected so as to reduce a norm of a nonlinear residual rm+1 employed in a subsequent step.
Type: Application
Filed: February 19, 2003
Publication date: August 26, 2004
Applicants: Kazuo Kikuchi, VINAS Co., Ltd.
Inventors: Atsuhiro Tamura, Kazuo Kikuchi, Akihiro Ida
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Delta-phase detection method and system
Publication number: 20050207517
Abstract: A delta-phase detection method for real-time identifying a burst sequence in a received signal. The delta-phase detection method calculates phase differences between every two consecutive samples of the received signal, and counts the number of successive phase differences that are within a predetermined allowable detecting range. The end of the burst sequence is detected if the counting number is within a valid counting range. The valid counting range is determined according to an expected duration of the burst sequence. The frequency of the burst sequence can be calculated by a simple linear equation. A delta-phase detection system is also provided in the present invention, comprising a band pass filter, a delta-phase calculator, a low pass filter, and a flat line detector. The delta-phase detection system can be easily implemented in a digital signal processor of a mobile station to identify the FCCH burst sequence and compute the burst frequency.
Type: Application
Filed: March 17, 2004
Publication date: September 22, 2005
Inventor: Chunlan Qin
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Delta-phase detection method and system
Patent number: 7292660
Abstract: A delta-phase detection method for real-time identifying a burst sequence in a received signal. The delta-phase detection method calculates phase differences between every two consecutive samples of the received signal, and counts the number of successive phase differences that are within a predetermined allowable detecting range. The end of the burst sequence is detected if the counting number is within a valid counting range. The valid counting range is determined according to an expected duration of the burst sequence. The frequency of the burst sequence can be calculated by a simple linear equation. A delta-phase detection system is also provided in the present invention, comprising a band pass filter, a delta-phase calculator, a low pass filter, and a flat line detector. The delta-phase detection system can be easily implemented in a digital signal processor of a mobile station to identify the FCCH burst sequence and compute the burst frequency.
Type: Grant
Filed: March 17, 2004
Date of Patent: November 6, 2007
Assignee: Via Technologies, Inc.
Inventor: Chunlan Qin
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Electronic speed rating calculator and method
Patent number: 4133031
Abstract: Apparatus and method are set forth for calculating a comparative speed rating for an entrant in a race such as a horserace so that the entrants performance can be compared with the performance of other entrants. The speed rating is determined in accordance with a formula which is based on a linear relationship between speed and distance over a particular distance for a particular class of entrant and where the speed rating for an entrant other than the winner is determined over the actual distance covered by the non-winning entrant in the same time as the winner. The specific equation to determine the speed rating is as follows: ##EQU1## Where f is the length of the race in furlongs Where L is the number of lengths horse was behind the winnerWhere t is the time of the winner in seconds.
Type: Grant
Filed: April 20, 1977
Date of Patent: January 2, 1979
Assignee: Esrac Computer Corporation
Inventor: Robert S. Sinn
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Current Control Semiconductor Element and Control Device Using the Same
Publication number: 20130147453
Abstract: This invention provides a current control semiconductor element that can detect a current with high accuracy in a single IC chip by dynamically correcting changes in a gain a and an offset b, and a control device that uses the current control semiconductor element. The current control semiconductor element has a transistor 4, a current-to-voltage conversion circuit 22 and an AD converter 23 on the same semiconductor chip. A reference current generation circuit 6 superimposes a current pulse Ic on a current of a load 2 and changes a voltage digital value to be output from the AD converter. A gain/offset corrector 8 executes signal processing on change in the voltage digital value caused by the reference current generation circuit 6 to dynamically acquire the gain a and the offset b that are used in an equation that indicates a linear relationship between the voltage digital value output from the AD converter 23 and the current digital value of the load.
Type: Application
Filed: August 1, 2011
Publication date: June 13, 2013
Applicant: HITACHI AUTOMOTIVE SYSTEMS, lTD.
Inventors: Teppei Hirotsu, Nobuyasu Kanekawa, Itaru Tanabe
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Current control semiconductor element and control device using the same
Patent number: 9170587
Abstract: This invention provides a current control semiconductor element that can detect a current with high accuracy in a single IC chip by dynamically correcting changes in a gain a and an offset b, and a control device that uses the current control semiconductor element, the current control semiconductor element has a transistor 4, a current-to-voltage conversion circuit 22 and an AD converter 23 on the same semiconductor chip. A reference current generation circuit 6 superimposes a current pulse Ic on a current of a load 2 and changes a voltage digital value to be output from the AD converter. A gain/offset corrector 8 executes signal processing on change in the voltage digital value caused by the reference current generation circuit 6 to dynamically acquire the gain a and the offset b that are used in an equation that indicates a linear relationship between the voltage digital value output from the AD converter 23 and the current digital value of the load.
Type: Grant
Filed: August 1, 2011
Date of Patent: October 27, 2015
Assignee: Hitachi Automotive Systems, Ltd.
Inventors: Teppei Hirotsu, Nobuyasu Kanekawa, Itaru Tanabe
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Method and apparatus for semiconductor device simulation with linerly changing quasi-fermi potential, medium storing program for the simulation, and manufacturing method for the semiconductor device
Patent number: 6304834
Abstract: A semiconductor device simulator having a grid generator, a quasi-Fermi potential setting unit, a bias setting unit, a coefficient matrix and residual vector setting unit and a matrix calculator is disclosed. A grid generator defines a finite number of grid points inside and around a semiconductor device, and generates a plurality of grids. A quasi-Fermi potential setting unit sets said linear quasi-Fermi potentials, which is linearly changing, at each section inside the generated grid. A bias setting unit defines the terminal bias to be applied to predetermined electrode regions. A coefficient matrix and residual vector setting unit obtains carrier concentration inside each grid from the quasi-Fermi potential, and sets coefficient matrix/residual vector for the basic equations. A matrix calculator calculates this coefficient matrix, and accordingly obtains the solution for the Poisson's equation and the carrier continuity equations to obtain the device behavior.
Type: Grant
Filed: September 14, 1999
Date of Patent: October 16, 2001
Assignee: Kabushiki Kaisha Toshiba
Inventor: Toshiyuki Enda
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Echo canceller with means for determining filter coefficients from autocorrelation and cross-correlation coefficients
Patent number: 5062102
Abstract: In a data transmission system where a first signal partially leaks as an echo from a first transmission line to a second transmission line through a hybrid circuit to form a mixed signal of the echo and a second signal on the second transmission line, an echo canceller is used for cancelling the echo by producing an echo replica at a transversal filter according to filter coefficients and subtracting the echo replica from the mixed signal. In order to reliably generate the filter coefficient for a reduced time duration, a series of autocorrelation coefficients of the first signal and a series of cross-correlation coefficients between the first and the mixed signals are calculated at calculators and the filter coefficients are determined from both of the autocorrelation and the cross-correlation coefficient series at a coefficient determining circuit. The coefficient determining circuit may be an arithmetic circuit for solving simultaneous linear equations.
Type: Grant
Filed: December 1, 1989
Date of Patent: October 29, 1991
Assignee: NEC Corporation
Inventor: Tetsu Taguchi
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Arithmetic pipeline for image processing
Patent number: 4700319
Abstract: The arithmetic pipeline processor (which is used for computer graphics such as a flight simulator) is a group of boards capable of solving an equation of the formA.sup.m B.sup.n +C.sup.o D.sup.P +E.sup.q F.sup.r +G.sup.s H.sup.twhere A, B, C, D, E, F, G, H are 32-bit implied one floating point numbers, and m, n, o, p, q, r, s, t can take on the values 1/4, 1/2, 1, 2 and 0. It includes a digital logarithmic calculator using shifters and stored tables to perform arithmetic functions such as multiplication, division, squares, square roots, and fourth roots. It comprises two input ports each capable of receiving digital data N bits wide. Included are a log transform unit, a log sum or difference unit and an antilog unit. Following these is an M-bit Aritmetic Logic Unit (ALU) and circuitry for converting between fixed point and floating point numbers. It uses piece wise linear approximation in conjunction with stored slope information in tables to do the transform calculation of logarithms and antilogarithms.
Type: Grant
Filed: June 6, 1985
Date of Patent: October 13, 1987
Assignee: The United States of America as represented by the Secretary of the Air Force
Inventor: Walter R. Steiner
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